IMT Atlantique, internationally recognised for the quality of its research, is a leading general engineering school under the aegis of the Ministry of Industry and Digital Technology, ranked in the three main international rankings (THE, SHANGHAI, QS).
Located on three campuses, Brest, Nantes and Rennes, IMT Atlantique aims to combine digital technology and energy to transform society and industry through training, research and innovation. It aims to be the leading French higher education and research institution in this field on an international scale. With 290 researchers and permanent lecturers, 1000 publications and 18 M€ of contracts, it supervises 2300 students each year and its training courses are based on cutting-edge research carried out within 6 joint research units: GEPEA, IRISA, LATIM, LABSTICC, LS2N and SUBATECH.
The Mathematical and Electrical Engineering (MEE) Department: Resulting from the merger of the Electronics (ELEC) and Signal & Communications (SC) departments, the new Mathematical and Electrical Engineering (MEE) department relies on the multidisciplinary expertise of its 37 permanent staff and faculty members. Involved in teaching as well as research, the MEE department brings together specialists in the fields of digital communications, data science and artificial intelligence, as well as in the design of embedded circuits and solutions.
Team: The ANR funded young researcher program or “JCJC” project “TurboLEAP”, which started in March 2021 and is led by Stefan Weithoffer, will investigate the design of ultra-high throughput hardware architectures for the decoding of Turbo codes, focusing jointly on code-, decoding-algorithm- and hardware-design aspects. Within TurboLEAP, the Post-Doctoral Fellow is expected to closely interact with the PhD candidate also funded by the TurboLEAP project and who is focusing on hardware design aspects. In collaboration with well-established researchers in the field of Turbo coding/decoding and hardware implementations, mainly associate professors Charbel Abdel Nour and Stefan Weithoffer, he will also work in close collaboration with a second PhD candidate planned to be recruited in the context algorithm design. Together, the assembled team shall achieve the required level of synergy between the simplified design of decoding algorithms and their impact on hardware implementations.
Forward Error Correction based on Turbo codes enabled the mobile internet and ubiquitous video streaming with third and fourth generation (3G/4G) wireless communication systems. However, the widespread use of Turbo codes and the low level of targeted rates led to only a few decoding algorithms being considered for practical use cases. The BCJR/MAP algorithm and its variants in the logarithmic domain represent the standard algorithms used in software and hardware implementations. This textbook knowledge has not been significantly challenged in almost 30 years. As a consequence, however, ultra-high throughput implementations are not practically feasible with current Turbo decoder hardware architectures which merely offer a maximum throughput in the order of single digit Gb/s or require large amounts of chip area. TurboLEAP aims at making substantial contributions towards decoding Turbo codes at Tb/s. The road to Tb/s Turbo decoders goes through the joint introduction of profound modifications to their decoding algorithm and to their code design while taking into account implementation and application constraints.
The objective of this Post Doctoral fellowship is to contribute to the TurboLEAP project on the code design of fast converging codes as well as spatially coupled Turbo codes suited for hardware implementations.
PhD of less than 3 years in Communications Engineering, Electrical Engineering or similar
A solid knowledge about Forward Error Correction schemes, in particular Turbo Codes and/or LDPC codes.
Experience with spatial coupling schemes (Spatially Coupled- LDPC codes, Turbo-like codes, Braided Codes) is a plus.
Furthermore, competences in terms of code- or decoding algorithm-design are beneficial.
A familiarity with hardware design and/or FEC decoder hardware architectures is not required but beneficial to facilitate seamless discussions of interdisciplinary nature with other team members, enabling a joint Code-, Algorithm- and Hardware-Design.
The candidate should be comfortable to work with an existing environment for code design written mainly in C/C++ and extend it as required for the objective of the fellowship.
Experience with one or more of the following languages: C, C++, Python
Experience with code- or algorithm design for wireless communications
Advanced lectures on channel coding and communication systems